I347-AT4 Datasheet, PDF (70/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Device Functionality
3.24.5
VDDOR
VDDOR supplies the digital I/O pins for TDO, TDI, TMS, TCK, TRSTn, REF_CLKP/N, or
CLK_SEL[1:0].
V18_R should be tied to VSS if the VDDOR voltage is set to 3.3V.
V18_R should be floating if the VDDOR voltage is set to 1.9V.
3.24.6
VDDOM
VDDOM supplies the digital I/O pins for MDC, MDIO, and TEST.
V12_EN should be tied to VSS if the VDDOM voltage is set to 3.3V.
V12_EN should be floating if the VDDOM voltage is set to 1.9V.
3.24.7
Power Supply Sequencing
On power-up, no special power supply sequencing is required.
3.25
Clocking Support
There two components to clocking support: Recovered Clock and Reference Clock
Select. The first is to output a recovered clock. The second is to select between the
local reference clock and a cleaned-up recovered clock.
3.25.1
Recovered Clock
The RCLK1 and RCLK2 pins of the chip outputs either a 125 MHz or 25 MHz clock that is
based on the 125 MHz recovered clock on the copper receive path when linked to
1000BASE-T or 100BASE-TX. If a 25 MHz clock is selected, the 125 MHz recovered
clock is internally divided by 5 with 60% low and 40% high.
Register 16_2.11 selects whether RCLK outputs 25 MHz XTAL clock or drives LOW when
the link is down or when the copper receiver is linked to 10BASE-T.
• 0b = RCLK outputs 25 MHz XTAL clock during link down or 10BASE-T
• 1b = RCLK drives LOW during link down or 10BASE-T
RCLK1 pin is enabled when register 16_2.8 is set to 1b, and RCLK2 pin is enabled when
register 16_2.9 is set to 1b. Each of these bits should be set to 1b for only one port
(16_2.8 set to 1b in port 0 and 16_2.9 set to 1b for port 1). If the bit is set high for
multiple ports then the highest numbered physical port that is enabled is selected. The
highest numbered physical port is defined to be the port connected to MDIP/N3 and not
necessarily the port with the highest PHYAD[4:0] value. (the PHY_ORDER setting
affects the PHYAD[1:0] setting.)
Register 16_2.12 selects whether RCLK 25 MHz outputs 25 MHz or 125 MHz. 0b = 25
MHz, 1 = 125 MHz.
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