I347-AT4 Datasheet, PDF (127/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Electrical and Timing Specifications—I347-AT4
MDI 1000
100
10
SSD1
SSD2
/J/
/K/
PREAMBLE
S_OUTP/N
T _{AS_MDI_SERTX}
1ST /S/
/S/
(CSExtend, CSExtend_Err)
CSReset
/T/
/R/
ETD
T _{DA_MDI_SERTX}
1ST /T/
/T/
Figure 32. 10/100/1000BASE-T-to-SGMII Latency Timing
5.9.2
SGMII to 10/100/1000BASE-T Latency Timing
Over a full range of values listed in Section 5.1 unless otherwise specified.
Symbol
Parameter
Condition
Min
Typ
Max
Units
T_{AS_SERRX_MDI_}
1000
T_{DA_SERRX_MDI_}
1000
S_INP/N Start of Packet /S/
to MDI SSD1
S_INP/N /T/ to MDI
CSReset, CSExtend,
CSExtend_Err
192¹
192^1,2
216
ns
216
ns
T_{AS_SERRX_MDI_}
100
S_INP/N Start of Packet /S/
to MDI /J/
528¹
612
ns
T_{DA_SERRX_MDI_}
100
S_INP/N /T/ to MDI /T/
528^1,2
612
ns
T_{AS_SERRX_MDI_}
10
S_INP/N Start of Packet /S/
to MDI Preamble
3822¹
4634
ns
T_{DA_SERRX_MDI_}
10
S_INP/N /T/ to MDI ETD
3822^1,2
4634
ns
1. Assumes register 16.15:14 is set to 00b, which is the minimum latency. Each increase in setting adds 8 ns of latency in
1000 Mb/s, 40 ns in 100 Mb/s, and 400 ns in 10 Mb/s.
2. Minimum and maximum values on end of packet assume zero frequency drift between the transmitted signal on MDI and the
received signal on S_INP/N. The worst case variation is outside these limits, if there is a frequency difference.
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