I347-AT4 Datasheet, PDF (108/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

I347-AT4—Programmer’s Visible State
4.1.53 General Control Register - Page 6, Register 20
Bits
Field
15
Reset
14:12 Reserved
11:10 Snooping
9
Reserved
8
Reserved
7
Reserved
6
Reserved
5:4
Preferred Media
3
Reserved
2:0
MODE[2:0]
Mode HW Rst SW Rst
Description
R/W, SC 0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0
0x0
0x1
See
Descr.
See
Descr.
0x0
0x0
R/W
0x0
See
Descr.
R/W
0x0
SC
Retain
Retain
Retain
Retain
Mode Software Reset. Affects page 6.
Writing a 1 to this bit causes the main PHY state machines to
be reset. When the reset operation is done, this bit is cleared
to 0 automatically. The reset occurs immediately.
1 = PHY reset
0 = Normal operation
Set to 0s
00 = Turn off Snooping
01 = Reserved
10 = Snoop data from network
11 = Snoop data from MAC
Reservedp
Reserved
Retain
Retain
Retain
Update
Update
0x0
Reserved
Set to 0
00 = Link on first media
01 = Copper Preferred
10 = Reserved
11 = Reserved
0 = Normal operation
1 = Reserved.
Changes to this bit are disruptive to the normal operation;
therefore, any changes to these registers must be followed
by a software reset to take effect.
On hardware reset these bits take on the value of
MODE[2:0].
000 = Reserved
001 = SGMII (System mode) to Copper
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
4.1.54 Late Collision Counters 1 & 2 - Page 6, Register 23
Bits
15:8
Field
Mode
Late Collision 97-
128 bytes
RO, SC
HW Rst SW Rst
Description
0x00
Retain
This counter increments by 1 when the PHY is in half-duplex
and a start of packet is received while the 97th to 128th
bytes of the packet are transmitted.
The measurement is done at the internal GMII interface. The
counter will not roll over and will clear on read.
98