I347-AT4 Datasheet, PDF (65/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Device Functionality—I347-AT4
3.21.1
Table 29.
Hardware Configuration
After the deassertion of RESETn, the I347-AT4 is hardware configured.
The I347-AT4 is configured through the CONFIG[3:0] pins and CLK_SEL[1:0].
CLK_SEL[1:0] are used to select the reference clock input option as well as the serial
LED feature:
CLK_SEL[1:0] Configuration Settings
Table 30.
CLK_SEL[1:0]
10b
Clock Input
25 MHz XTAL_IN/XTAL_OUT
11b
25 MHz XTAL_IN/XTAL_OUT
SER_LED
0b
1b
0b
1b
SER_LED Feature
Not supported
Not supported
Not supported
Each CONFIG[3:0] pin is used to configure four bits. The 4-bit value is set depending
on what is connected to the CONFIG pins soon after the deassertion of hardware reset.
The 4-bit mapping is shown in Table 30.
Four Bit Mapping
Pin
VSS
P0_LED[1]
P0_LED[2]
P0_LED[3]
P1_LED[0]
P1_LED[1]
P1_LED[2]
P1_LED[3]
P2_LED[0]
P2_LED[1]
P2_LED[2]
P2_LED[3]
P3_LED[0]
P3_LED[1]
P3_LED[2]
VDDO
P0_LED[0]
P3_LED[3]
Bit 3, 2,1,0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reserved
Reserved
The four bits for each CONFIG pin is mapped as listed in Table 30. CONFIG[2:1] are
reserved and should not be used as configuration pins.
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