I347-AT4 Datasheet, PDF (47/148 Pages) Intel Corporation – Intel® Ethernet Network Connection I347-AT4 Datasheet

Device Functionality—I347-AT4
Table 15. Registers for DTE Power
3.12
Register
Description
26_0.8 - Enable power over Ethernet
detection
17_0.2 - Power over Ethernet
detection status
19_0.2 - Power over Ethernet
detection state changed
26_0.7:4 - DTE detect status drop
1b = Enable DTE detect.
0b = Disable DTE detect.
A soft reset is required to enable this feature.
Hardware reset: 0b.
Software reset: Update.
1b = Need power.
0b = Do not need power.
Hardware reset: 0b.
Software reset: 0b.
1b = Changed.
0b = No change.
Hardware reset: 0b.
Software reset: 0b.
Once the PHY no longer detects that the link partner filter, the PHY
waits a period of time before clearing the power over Ethernet
detection status bit (17_0.2).
The wait time is 5 seconds multiplied by the value of these bits.
Example: (5 * 0x4 = 20 seconds).
Default at hardware reset: 0x4.
At software reset: retain.
CRC Error Counter and Frame Counter
The CRC counter and frame counters, normally found in MACs, are available in the
I347-AT4. The error counter and frame counter features are enabled through register
writes and each counter is stored in eight register bits.
Register 18_6.2:0 controls which path the CRC checker and packet counter is counting.
If register 18_6.2:0 is set to 010b then the copper receive path is checked.
3.12.1
Enabling The CRC Error Counter and Frame Counter
To enable both counters to count, set 18_6.2:0 to a non-zero value.
To disable and clear both counters, set 18_6.2:0 to 000b.
To read the CRC counter and frame counter, read register 17_6.
17_6.15:8 (Frame count is stored in these bits).
17_6.7:0 (CRC error count is stored in these bits).
The CRC counter and frame counter do not clear on a read command. To clear the
counters, disable/reset the CRC checker by writing Reg 18_6.2:0 = 000b.
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