82845PE Datasheet, PDF (93/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.3.9
HDR2—Header Type Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
0Eh
00h
RO
8 bits
This register contains the Header Type of the IGD.
3.5.3.10
Bit
Description
7:0
Header Code (H). This is an 8-bit value that indicates the Header Code for the IGD.
00h = Single function device with a type 0 configuration space format.
GMADR —Graphics Memory Range Address Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
10−13h
00000008h
R/W, RO
32 bits
This register requests allocation for the IGD graphics memory. The allocation is for either 64 MB
or 128 MB and the base address is defined by bits [31:27,26].
Bit
31:27
26
25:4
3
2:1
0
Description
Memory Base Address—R/W. Set by the operating system. These bits correspond to address
signals [31:26].
128MB Address Mask—RO, R/W. The operation of this bit is controlled via Device 0 register
GCCR. If the signal is low this bit is Read Only with a value of 0, indicating a memory range of
128 MB. If the signal is high, this bit becomes R/W, indicating a memory range of 64 MB (where
system software will program the bit to the appropriate address bit value).
Address Mask—RO. Hardwired to zeros to indicate (at least) a 32-MB address range.
Prefetchable Memory—RO. Hardwired to 1 to enable prefetching.
Memory Type—RO. Hardwired to 0 to indicate 32-bit address.
Memory/IO Space—RO. Hardwired to 0 to indicate memory space.
Intel^® 82845GE/82845PE Datasheet
93