82845PE Datasheet, PDF (53/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.1.10 APBASE—Aperture Base Configuration Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
10–13h
00000008h
RO, R/W
32 bits
The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics
Aperture. The standard PCI Configuration mechanism defines the base address configuration
register such that only a fixed amount of space can be requested (dependent on which bits are
hardwired to 0 or behave as hardwired to 0). To allow for flexibility (of the aperture) an additional
register called APSIZE is used as a “back-end” register to control which bits of the APBASE will
behave as hardwired to 0. This register will be programmed by the (G)MCH specific BIOS code
that will run before any of the generic configuration software is run.
Note: Bit 1 of the AGPM register is used to prevent accesses to the aperture range before this register is
initialized by the configuration software and the appropriate translation table structure has been
established in the main memory.
Bit
31:28
27:22
21:4
3
2:1
0
Description
Upper Programmable Base Address (UPBITS)—R/W. These bits are part of the aperture base set
by configuration software to locate the base address of the graphics aperture. They correspond to
bits [31:28] of the base address in the processor’s address space that will cause a graphics aperture
translation to be inserted into the path of any memory read or write.
Middle Hardwired/Programmable Base Address (MIDBITS)—R/W. These bits are part of the
aperture base set by configuration software to locate the base address of the graphics aperture.
They correspond to bits [27:4] of the base address in the processor’s address space that will cause a
graphics aperture translation to be inserted into the path of any memory read or write. These bits can
behave as though they were hardwired to 0 if programmed to do so by the APSIZE bits of the
APSIZE register. This will cause configuration software to understand that the granularity of the
graphics aperture base address is either finer or more coarse, depending upon the bits set by
(G)MCH-specific configuration software in APSIZE.
Lower Bits (LOWBITS)—RO. Hardwired to zeros. This forces the minimum aperture size selectable
by this register to be 4 MB, without regard to the aperture size definition enforced by the APSIZE
register.
Prefetchable (PF)—RO. Hardwired to 1. This identifies the Graphics Aperture range as prefetchable
(per the PCI Local Bus Specification, Revision 2.1 for base address registers). This implies that there
are no side effects on reads, the device returns all bytes on reads (regardless of the byte enables)
and the (G)MCH may merge processor writes into this range without causing errors.
Addressing Type (TYPE)—RO. Hardwired to 00. This indicates that the address range defined by
the upper bits of this register can be located anywhere in the 32-bit address space as per the PCI
Local Bus Specification, Revision 2.1 for base address registers.
Memory Space Indicator (MSPACE)—RO. Hardwired to 0. This identifies the aperture range as a
memory range as per the PCI Local Bus Specification, Revision 2.1 for base address registers.
Intel^® 82845GE/82845PE Datasheet
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