82845PE Datasheet, PDF (31/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Signal Description
Name
DVOC_BLANK#
DVOBC_INTR#
DVOC_FLDSTL
MI2C_CLK
MI2C_DATA
MDVI_CLK
MDVI_DATA
MDDC_CLK
MDDC_DATA
ADDID[7:0]
Type
Description
O
AGP
Flicker Blank or Border Period Indication: DVOC_BLANK# is a
programmable output pin driven by the GMCH. When programmed as a
blank period indication, this signal indicates active pixels excluding the
border. When programmed as a border period indication, this signal indicates
active pixel including the border pixels.
I
AGP
DVOBC Interrupt: This signal may be used as an interrupt input for either of
the multiplexed DVO devices.
I
AGP
TV Field and Flat Panel Stall Signal: This input can be programmed to be
either a TV Field input from the TV encoder or Stall input from the flat panel.
When used as a Field input, it synchronizes the overlay field with the TV
encoder field when the overlay is displaying an interleaved source. When
used as the Stall input, it indicates that the pixel pipeline should stall one
horizontal line. The polarity is programmable for both modes and the input
may be disabled completely.
I/O AGP
MI2C_CLK: The specific function of this signal is I2C_CLK for a multiplexed
digital display. This signal is tri-stated during a hard reset.
I/O
AGP
MI2C_DATA: The specific function of this signal is I2C_DATA for a
multiplexed digital display. This signal is tri-stated during a hard reset.
I/O
AGP
MDVI_CLK: The specific function is DVI_CLK (DDC) for a multiplexed digital
display connector. This signal is tri-stated during a hard reset.
I/O
AGP
MDVI_DATA: The specific function of this signal is DVI_DATA (DDC) for a
multiplexed digital display connector. This signal is tri-stated during a hard
reset.
I/O
AGP
MDDC_CLK: This signal may be used as the DDC_CLK for a secondary
multiplexed digital display connector. This signal is tri-stated during a hard
reset.
MDDC_DATA: This signal may be used as the DDC_Data for a secondary
I/O AGP multiplexed digital display connector. This signal is tri-stated during a hard
reset.
I/O
AGP
ADD Card ID: These signals will be strapped on the ADD card for software
identification purposes. These signals may need pull-up or pull-down
resistors in a DVO device down scenario.
Intel^® 82845GE/82845PE Datasheet
31