82845PE Datasheet, PDF (59/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.1.17
DRA—DRAM Row Attribute Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
70–71h (72–77h Reserved)
00h
R/W
8 bits
The DRAM Row Attribute Register defines the page sizes to be used when accessing different
pairs of rows. Each nibble of information in the DRA registers describes the page size of a pair of
rows:
Row0, 1: 70h
Row2, 3: 71h
76
432
0
R
Row Attribute for Row 1
R
Row Attribute for Row 0
76
432
0
R
Row Attribute for Row 3
R
Row Attribute for Row 2
Bit
Description
7 Reserved.
Row Attribute for Odd-numbered Row. This field defines the page size of the corresponding row.
000 = 2 KB
6:4
001 = 4 KB
010 = 8 KB
011 = 16 KB
Others = Reserved
3 Reserved.
Row Attribute for Even-numbered Row. This field defines the page size of the corresponding row.
000 = 2 KB
2:0
001 = 4 KB
010 = 8 KB
011 = 16 KB
Others = Reserved
Intel^® 82845GE/82845PE Datasheet
59