82845PE Datasheet, PDF (26/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Signal Description
2.3
Hub Interface
2.4
2.4.1
Signal
Name
HI_[10:0]
HI_STBS
HI_STBF
Type
Description
I/O
sts
Hub Interface Signals: HI_[10:0] are used for the hub Interface.
I/O
Hub Interface Strobe: HI_STBS is one of two differential strobe signals used to
sts
transmit or receive packet data over the hub Interface.
I/O
Hub Interface Strobe Complement: HI_STBF is one of two differential strobe
sts
signals used to transmit or receive packet data over the hub Interface.
AGP Interface Signals
AGP Addressing Signals
Signal Name
GPIPE#
GSBA[7:0]
Type
I
AGP
I
AGP
Description
Pipelined Read: This signal is asserted by the current master to indicate a full
width address is to be queued by the target. The master queues one request each
rising clock edge while GPIPE# is asserted. When GPIPE# is deasserted, no new
requests are queued across the GAD bus.
GPIPE# is a sustained tri-state signal from the master (graphics controller) and is
an input to the (G)MCH.
Sideband Address: This bus provides an additional bus to pass addresses and
commands to the (G)MCH from the AGP master.
Note:
The above table contains two mechanisms to queue requests by the AGP master. Note that the
master can only use one mechanism. When PIPE# is used to queue addresses, the master is not
allowed to queue addresses using the sideband (SB) bus. During configuration time, if the master
indicates that it can use either mechanism, the configuration software indicates which mechanism
the master will use. Once this choice has been made, the master continues to use the mechanism
selected until the master is reset (and reprogrammed) to use the other mode. This change of modes
is not a dynamic mechanism but rather a static decision when the device is first being configured
after reset.
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Intel^® 82845GE/82845PE Datasheet