82845PE Datasheet, PDF (119/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Functional Description
Memory Read Line, and Memory Read Multiple: These commands are treated identically
by the (G)MCH. The (G)MCH issues two snoops (a snoop followed by a snoop-ahead) on the host
bus and releases the processor bus for other traffic. When the first DWord of the first cache line is
delivered and GFRAME# is still asserted, the (G)MCH issues another snoop-ahead on the host bus.
This allows the (G)MCH to continuously supply data during memory read line and memory read
multiple bursts. When the transaction terminates, there may be a minimum of 2 cache lines and a
maximum of 2 cache lines plus 7 DWords buffered. Subsequent memory reads hitting the buffers
will return data from the buffer.
Memory Write and Memory Write and Invalidate: These commands are aliased and
processed identically. The (G)MCH supports data streaming for PCI-to-DRAM writes based on its
ability to buffer up to 128 bytes (16 QWords) of data before a snoop cycle must be completed on
the host bus. The (G)MCH is typically able to support longer write bursts, with the maximum
length dependent upon concurrent host bus traffic during PCI-DRAM write data streaming.
Fast Back-to-Back Transactions: The (G)MCH, as a target, supports fast back-to-back cycles
from a PCI initiator. As a PCI initiator, the (G)MCH is responsible for translating host cycles to
AGP/PCI_B cycles. The (G)MCH also transfers hub interface to AGP/PCI_B write cycles.
Table 5-7 shows all the cycles that need to be translated.
Table 5-7. PCI Commands Supported by (G)MCH When Acting As an AGP/PCI_B Initiator
Source Bus
Command
Other Encoded Information
(G)MCH Host Bridge
Corresponding
PCI_B Command
GC/BE[3:0]#
Encoding
Source Bus: Host
Deferred Reply
Interrupt Acknowledge
Special Cycle
Don’t Care
Length ≤ 8 Bytes
Shutdown
Halt
Stop Clock Grant
All Other Combinations
Branch Trace Message
I/O Read
I/O Write
I/O Read to 0CFCh
I/O Write to 0CFCh
Memory Read (Code or
Data)
Memory Read
Invalidate
Memory Write
Locked Access
None
Length ≤ 8 Bytes up to 4 BEx Asserted
Length ≤ 8 Bytes up to 4 BEx Asserted
Length ≤ 8 Bytes up to 4 BEx Asserted
Length ≤ 8 Bytes up to 4 BEx Asserted
Length < 8 Bytes without All BEs Asserted
Length = 8 Bytes with All BEs Asserted
Length = 16 Bytes
Length = 32 Bytes Code Only
Length < 8 Bytes without All BEs Asserted
Length = 16 Bytes
Length = 32 Bytes
All Combinations
Reserved Encodings All Combinations
None
None
None
None
None
None
None
I/O Read
I/O Write
Configuration Read
Configuration Write
Memory Read
Memory Read
None
Memory Read
Memory Write
None
Memory Write
Unlocked Access¹
None
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0010
0011
1010
1011
0110
1110
N/A
1110
0111
N/A
0111
As Applicable
N/A
Intel^® 82845GE/82845PE Datasheet
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