82845PE Datasheet, PDF (79/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.2.6
3.5.2.7
3.5.2.8
SUBC1—Sub-Class Code Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Ah
04h
RO
8 bits
This register contains the Sub-Class Code for the (G)MCH Device 1.
Bit
Description
Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge into which the
7:0 ^{Device 1 of the (G)MCH falls.}
04h = PCI-to-PCI bridge.
BCC1—Base Class Code Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Bh
06h
RO
8 bits
This register contains the Base Class Code of the (G)MCH Device 1.
Bit
Description
Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the
7:0 ^{(G)MCH Device 1.}
06h = Bridge device.
MLT1—Master Latency Timer Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
RO, R/W
8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a
read/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.”
Bit
Description
7:3
Scratchpad MLT (NA7.3). These bits return the value with which they are written; however, they
have no internal function and are implemented as a scratchpad merely to avoid confusing software.
2:0 Reserved.
Intel^® 82845GE/82845PE Datasheet
79