82845PE Datasheet, PDF (25/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Signal Description
2.2
DDR SDRAM Interface
Signal Name
SCMDCLK_[5:0]
SCMDCLK_[5:0]#
SCS_[3:0]#
SMAA_[12:0],
SMAB_[5,4,2,1]
SBA[1:0]
SRAS#
SCAS#
SWE#
SDQ_[63:0]
SDM_[7:0]
SDQS_[7:0]
SCKE_[3:0]
SRCVEN_OUT#
SRCVEN_IN#
Type
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_2
I/O
SSTL_2
O
SSTL_2
I/O
SSTL_2
O
SSTL_2
O
SSTL_2
I
SSTL_2
Description
Differential DDR Clock: SCMDCLK_x and SCMDCLK_x# pairs are
differential clock outputs. The crossing of the positive edge of SCMDCLK_x
and the negative edge of SCMDCLK_x# is used to sample the address and
control signals on the SDRAM. There are 3 pairs to each DIMM.
Complementary Differential DDR Clock: These are the complementary
Differential DDR Clock signals.
Chip Select: These signals select particular SDRAM components during
the active state. There is one SCS# for each SDRAM row, toggled on the
positive edge of SCMDCLK.
Memory Address: These signals provide the multiplexed row and column
address to the SDRAM. SMAB_[5,4,2,1] signals are selective CPC signals
and are identical to SMAA_[5,4,2,1].
Bank Select (Bank Address): These signals define which banks are
selected within each SDRAM row. Bank select and memory address signals
combine to address every possible location within an SDRAM device.
Row Address Strobe: SRAS# is used with SCAS# and SWE# (along with
SCS#) to define the SDRAM commands.
Column Address Strobe: SCAS# is used with SRAS# and SWE# (along
with SCS#) to define the SDRAM commands.
Write Enable: SWE# is used with SCAS# and SRAS# (along with SCS#) to
define the SDRAM commands.
Data Lines: SDQ_[63:0] interface to the SDRAM data bus.
Data Mask: When activated during writes, the corresponding data groups in
the SDRAM are masked. There is one SDM for every eight data lines. SDM
can be sampled on both edges of the data strobes.
Data Strobes: Data strobes are used for capturing data. During writes,
SDQS is centered in data. During reads, SDQS is edge aligned with data.
The following list matches the data strobe with the data bytes.
SDQS_7 = SDQ_[63:56]
SDQS_6 = SDQ_[55:48]
SDQS_5 = SDQ_[47:40]
SDQS_4 = SDQ_[39:32]
SDQS_3 = SDQ_[31:24]
SDQS_2 = SDQ_[23:16]
SDQS_1 = SDQ_[15:8]
SDQS_0 = SDQ_[7:0]
Clock Enable: SCKE is used to initialize DDR SDRAM during power-up and
to place all SDRAM rows into and out of self-refresh during Suspend-to-
RAM. SCKE is also used to dynamically power down inactive SDRAM rows.
There is one SCKE per SDRAM row, toggled on the positive edge of
SCMD_CLK.
Receive Enable Out: This signal is a feedback testpoint signal used to
enable the DQS input buffers during reads. This pin should be connect to
SRCVEN_IN through an un-populated backside resistor site.
Receive Enable In: This signal is a feedback testpoint signal used to
enable the DQS input buffers during reads.
Intel^® 82845GE/82845PE Datasheet
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