82845PE Datasheet, PDF(14/176 Page) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

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82845PE Datasheet, PDF (14/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

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Introduction

1.2

Term

MCH

Primary PCI

PSB

Scalable Bus

SDR

SDRAM

Secondary PCI

SSTL_2

Description

The Memory Controller Hub (MCH) component contains the processor interface, SDRAM

controller, and AGP interface. It communicates with the I/O Controller Hub 4 (ICH4) over

a proprietary interconnect called the hub interface.

The physical PCI bus that is driven directly by the ICH4 component. Communication

between the PCI and the (G)MCH occurs over the hub interface. Note that even though

the Primary PCI bus is referred to as PCI, it is not PCI Bus #0 from a configuration

standpoint.

Processor System Bus. This is the bus between the (G)MCH and processor (also referred

to as the Host, FSB, or processor bus).

Processor-to-(G)MCH interface. The Compatible Mode of the Scalable Bus is the P6 bus.

The Enhanced Mode of the Scalable Bus is the P6 Bus plus enhancements primarily

consisting of source synchronous transfers for address and data, and PSB interrupt

delivery. The IntelÂ® Pentium 4 processor implements a subset of Enhanced Mode.

Single Data Rate SDRAM.

Synchronous Dynamic Random Access Memory.

The physical PCI interface that is a subset of the AGP bus driven directly by the (G)MCH.

It supports a subset of 32-bit, 66 MHz PCI Local Bus Specification, Revision 2.1-

compliant components, but only at 1.5 V (not 3.3 V or 5 V).

Stub Series Terminated Logic for 2.5 V (DDR).