82845PE Datasheet, PDF (81/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.2.12
SUBUSN1—Subordinate Bus Number Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1Ah
00h
R/W
8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI_B/AGP. This
number is programmed by the PCI configuration software to allow mapping of configuration
cycles to PCI_B/AGP.
3.5.2.13
Bit
Description
Subordinate Bus Number (BUSN). This register is programmed by configuration software with the
7:0
number of the highest subordinate bus that lies behind the Device 1 bridge. When only a single PCI
device resides on the AGP/PCI_B segment, this register will contain the same value as the SBUSN1
register.
SMLT1—Secondary Bus Master Latency Timer Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1Bh
00h
RO, R/W
8 bits
This register control the bus tenure of the (G)MCH on AGP/PCI the same way Device 0 MLT
controls the access to the PCI_A bus.
Bit
Description
7:3 Secondary MLT Counter Value (MLT). Programmable, default = 0 (SMLT disabled)
2:0 Reserved.
Intel^® 82845GE/82845PE Datasheet
81