82845PE Datasheet, PDF (13/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Introduction
Introduction
1
This datasheet is for both the Intel^® 82845GE Graphics and Memory Controller Hub (GMCH) and
Intel^® 82845PE Memory Controller Hub (MCH) components. The 82845GE GMCH is part of the
Intel^® 845GE chipset and the 82845PE MCH is part of the Intel^® 845PE chipset. Each chipset
contains two main components: GMCH (MCH) for the host bridge and I/O Controller Hub for the
I/O subsystem. The GMCH (MCH) provides the processor interface, system memory interface,
hub interface, and additional interfaces in an 845GE / 845PE chipset desktop platform. Both the
845GE chipset and 845PE chipset use the 82801DB ICH4 for the I/O Controller Hub.
The difference between the 82845GE GMCH and 82845PE MCH is that the 82845GE contains an
internal graphics device and the 82845PE does not contain an internal graphics device.
Note: Unless otherwise specified, the information in this document applies to both the 82845GE GMCH
and 82845PE MCH. The term (G)MCH refers to both the 82845GE GMCH and 82845PE MCH.
1.1
Terminology
Term
Accelerated
Graphics Port
(AGP)
AGP/PCI
Chipset Core
DDR
Full Reset
GART
GMCH
Graphics Core
HI
Host
Intel^® ICH4
IGD
LVTTL
Description
This refers to the AGP/PCI_B interface on the (G)MCH. The (G)MCH AGP interface
supports only 1.5 V Accelerated Graphics Port Interface, Specification 2.0-compliant
devices using PCI (66 MHz), AGP 1X (66 MHz), 2X (133 MT/s) and
4X (266 MT/s) transfers. The (G)MCH does NOT support 3.3 V devices. PIPE# and SBA
addressing cycles and their associated data phases are generally referred to as AGP
transactions. FRAME# cycles are generally referred to as AGP/PCI transactions.
AGP/PCI in the document refers to AGP/PCI_B.
The (G)MCH internal base logic.
Double Data Rate SDRAM.
A Full (G)MCH Reset is defined in this document when RSTIN# is asserted.
Graphics Aperture Re-Map Table. Table in memory containing the page re-map
information used during AGP aperture address translations.
The Graphics and Memory Controller Hub (GMCH) component contains the processor
interface, SDRAM controller, AGP interface, and an integrated 3D/2D/display graphics
core. It communicates with the I/O Controller Hub 4 (ICH4) over a proprietary interconnect
called the hub interface.
The internal graphics related logic in the GMCH. Also known as the Integrated Graphics
Device (IGD).
Hub Interface. The proprietary hub interconnect that ties the (G)MCH to the ICH4. In this
document HI cycles originating from or destined for the primary PCI interface on the ICH4
are generally referred to as HI/PCI or simply HI cycles.
This term is used synonymously with processor or CPU.
Fourth generation I/O Controller Hub component.
Integrated Graphics Device. Graphics device integrated into the GMCH.
Low Voltage TTL.
Intel^® 82845GE/82845PE Datasheet
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