82845PE Datasheet, PDF (67/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.1.24
ACAPID—AGP Capability Identifier Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
A0–A3h
00200002h
RO
32 bits
This register provides standard identifier for AGP capability.
3.5.1.25
Bit
31:24
23:20
19:16
15:8
7:0
Description
Reserved.
Major AGP Revision Number (MAJREV). These bits provide a major revision number of
Accelerated Graphics Port interface Specification, Revision 2.0 to which this version of (G)MCH
conforms. This field is hardwired to value of 0010b (i.e., implying Rev 2.0).
Minor AGP Revision Number (MINREV). These bits provide a minor revision number of
Accelerated Graphics Port Interface Specification, Revision 2.0 to which this version of (G)MCH
conforms. This number is hardwired to value of 0000 which implies that the revision is 2.0. Together
with major revision number this field identifies the (G)MCH as an Accelerated Graphics Port
Interface Specification, Revision 2.0 compliant device.
Next Capability Poin.ter (NCAPTR): AGP capability is the last capability described via the
capability pointer mechanism and therefore these bits are hardwired to 0 to indicate the end of the
capability linked list.
AGP Capability ID (CAPID). This field identifies the linked list item as containing AGP registers.
This field has a value of 0000_0010b assigned by the PCI SIG.
AGPSTAT—AGP Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
A4–A7h
1F000217h
RO
32 bits
This register reports AGP device capability/status.
Bit
31:24
23:10
9
8:6
5
4
3
2:0
Description
Request Queue (RQ). This field is hardwired to 1Fh to indicate a maximum of 32 outstanding AGP
command requests can be handled by the (G)MCH. This field contains the maximum number of
AGP command requests the (G)MCH is configured to manage. Default =1Fh to allow a maximum of
32 outstanding AGP command requests.
Reserved.
Side Band Addressing Support (SBA). This bit indicates that the (G)MCH supports side band
addressing. It is hardwired to 1.
Reserved.
Greater Than Four Gigabyte Support (GT4GIG). This bit indicates that the (G)MCH does not
support addresses greater than 4 GB. It is hardwired to 0.
Fast Write Support (FW). This bit indicates that the (G)MCH supports Fast Writes from the
processor to the AGP master. It is hardwired to a 1.
Reserved.
Data Rate Support (RATE). After reset the (G)MCH reports its data transfer rate capability. Bit 0
identifies if the AGP device supports 1X data transfer mode, bit 1 identifies if AGP device supports
2X data transfer mode, bit 2 identifies if AGP device supports 4X data transfer.
Intel^® 82845GE/82845PE Datasheet
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