82845PE Datasheet, PDF (115/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Functional Description
5.3.1.2 AGP Target Operations
As an initiator, the (G)MCH does not initiate cycles using AGP enhanced protocols. The (G)MCH
supports AGP target interface to main memory only. The (G)MCH supports interleaved AGP and
PCI transactions. The Table 5-5 summarizes target operation support of (G)MCH for AGP masters.
Table 5-5. AGP Commands Supported by (G)MCH When Acting As an AGP Target
AGP Command
Read
Hi-Priority Read
Reserved
Reserved
Write
Hi-Priority Write
Reserved
Reserved
Long Read
Hi-Priority Long
Read
Flush
Reserved
Fence
Reserved
Reserved
Reserved
GC/BE[3:0]#
Encoding
0000
0000
0001
0000
0010
0011
0100
0100
0101
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
(G)MCH Host Bridge
Cycle Destination
Main Memory
Hub Interface
Main Memory
Hub Interface
N/A
N/A
Main Memory
Hub Interface
Main Memory
Hub Interface
N/A
N/A
Main Memory
Hub Interface
Main Memory
Hub Interface
(G)MCH
N/A
(G)MCH
N/A
N/A
N/A
Response As AGP Target
Low Priority Read
Complete with random data
High Priority Read
Complete with random data
No Response
No Response
Low Priority Write
Cycle goes to SDRAM with BEs inactive
High Priority Write
Cycle goes to SDRAM with BEs inactive -
does not go to hub interface
No Response
No Response
Low Priority Read
Complete locally with random data - does
not go to hub interface
High Priority Read
Complete with random data
Complete with QW of Random Data
No Response
No Response – Flag inserted in (G)MCH
request queue
No Response
No Response
No Response
NOTE: N/A refers to a function that is not applicable
As a target of an AGP cycle, the (G)MCH supports all the transactions targeted at main memory
and summarized in Table 5-5. The (G)MCH supports both normal and high priority read and write
requests. The (G)MCH does not support AGP cycles to the hub interface. AGP cycles do not
require coherency management and all AGP-initiator accesses to main memory using AGP
protocol are treated as non-snoopable cycles. These accesses are directed to the AGP aperture in
main memory that is programmed as either uncacheable (UC) memory or write combining (WC) in
the processor’s MTRRs.
Intel^® 82845GE/82845PE Datasheet
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