82845PE Datasheet, PDF (113/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Functional Description
5.2.3 Memory Address Translation and Decoding
The (G)MCH contains address decoders that translate the address received on the host bus or the
hub interface. Decoding and translation of these addresses vary with the four SDRAM types. Also,
the number of pages, page sizes, and densities supported vary with the type. The (G)MCH supports
64-Mb, 128-Mb, 256-Mb, and 512-Mb SDRAM devices. The multiplexed row/column address to
the SDRAM memory array is provided by the memory bank select and memory address signals.
These addresses are derived from the host address bus as defined by Table 5-4 for SDRAM
devices.
Table 5-4. Address Translation and Decoding
1 Meg
12 R
64 x 16
32 x 8 o 24 11 12 x[26] 15 14 13 24 23 22 21 20 19 18 17 16
x 4 bks
x2 w
2 Meg
12 R
64 x 8
64 x 9 o 25 13 12 x[26] 15 14 25 24 23 22 21 20 19 18 17 16
x 4 bks
x2 w
2 Meg
12 R
128 x 16
64 x 9 o 25 13 12 x[26] 15 14 25 24 23 22 21 20 19 18 17 16
x 4 bks
x2 w
4 Meg
13
256 x 16
128 x 9
x 4 bks
x2
R
o 26 13 12 26
w
15 14 25 24 23 22 21 20 19 18 17 16
4 Meg
12 R
128 x 8
128 x 10 o 26 14 13 x[27] 15 26 25 24 23 22 21 20 19 18 17 16
x 4 bks
x2 w
8 Meg
13 R
256 x 8
256 x 10 o 27 14 13 27
x 4 bks
x2 w
15 26 25 24 23 22 21 20 19 18 17 16
5.2.4
DRAM Performance Description
The overall memory performance is controlled by the DRAM timing register, pipelining depth used
in the (G)MCH, memory speed grade, and the type of SDRAM used in the system. In addition, the
exact performance in a system is also dependent on the total memory supported, external buffering,
and memory array layout. The most important contribution to overall performance by the system
memory controller is to minimize the latency required to initiate and complete requests to memory,
and to support the highest possible bandwidth (full streaming, quick turnarounds). One measure of
performance is the total flight time to complete a cache line request. A true discussion of
performance involves the entire chipset, not just the system memory controller.
Intel^® 82845GE/82845PE Datasheet
113