82845PE Datasheet, PDF (85/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.2.19
PMBASE1—Prefetchable Memory Base Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
24–25h
FFF0h
R/W
16 bits
This register controls the processor to PCI_B prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeros
when read. This register must be initialized by the configuration software. For the purpose of
address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1-MB boundary.
3.5.2.20
Bit
15:4
3:0
Description
Prefetchable Memory Address Base (PMBASE). This field corresponds to A[31:20] of the lower
limit of the address range passed by bridge Device 1 across AGP/PCI_B.
Reserved.
PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
26–27h
0000h
RO, R/W
16 bits
This register controls the processor to PCI_B prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes
when read. This register must be initialized by the configuration software. For the purpose of
address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1-MB aligned memory block. Note that prefetchable
memory range is supported to allow segregation by the configuration software between the
memory ranges that must be defined as UC and the ones that can be designated as a USWC
(i.e, prefetchable) from the processor perspective.
Bit
15:4
3:0
Description
Prefetchable Memory Address Limit (PMLIMIT). This field corresponds to A[31:20] of the upper
limit of the address range passed by bridge Device 1 across AGP/PCI_B.
Reserved.
Intel^® 82845GE/82845PE Datasheet
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