82845PE Datasheet, PDF (86/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.2.21
BCTRL1—Bridge Control Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
3Eh
00h
RO, R/W
8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI bridges.
The BCTRL1 provides additional control for the secondary interface (i.e., PCI_B/AGP) as well as
some bits that affect the overall behavior of the “virtual” PCI-to-PCI bridge embedded within the
(G)MCH (e.g., VGA compatible address ranges mapping).
Bit
Description
7
Fast Back-to-Back Enable (FB2BEN)—RO. Hardwired to 0. The (G)MCH does not generate fast
back-to-back cycles as a master on AGP.
6
Secondary Bus Reset (SRESET)—RO. Hardwired to 0. The (G)MCH does not support generation
of reset via this bit on the AGP.
Master Abort Mode (MAMODE)—RO. Hardwired to 0. This means when acting as a master on
5 AGP/PCI_B the (G)MCH will drop writes on the floor and return all ones during reads when a Master
Abort occurs.
4 Reserved.
VGA Enable (VGAEN)—R/W. This bit controls the routing of processor-initiated transactions
targeting VGA compatible I/O and memory address ranges.
3
0 = Disable.
1 = Enable.
ISA Enable (ISAEN)—R/W. This bit modifies the response by the (G)MCH to an I/O access issued
by the processor that targets ISA I/O addresses. This applies only to I/O addresses that are enabled
by the IOBASE and IOLIMIT registers.
0 = Disable (default). All addresses defined by the IOBASE and IOLIMIT for processor I/O
2
transactions are mapped to PCI_B/AGP.
1 = Enable. The (G)MCH does Not forward to PCI_B/AGP any I/O transactions addressing the last
768 bytes in each 1 KB block, even if the addresses are within the range defined by the IOBASE
and IOLIMIT registers. Instead of going to PCI_B/AGP these cycles will be forwarded to the hub
interface where they can be subtractively or positively claimed by the ISA bridge.
SERR Enable (SERREN)—RO. Hardwired to 0. This bit normally controls forwarding SERR# on the
1 secondary interface to the primary interface. The (G)MCH does not support the SERR# signal on the
AGP/PCI_B bus.
Parity Error Response Enable (PEREN)—R/W. This bit controls (G)MCH’s response to data phase
parity errors on PCI_B/AGP. G_PERR# is not implemented by the (G)MCH.
0 = Disable. Address and data parity errors on PCI_B/AGP are not reported via the (G)MCH HI
0
SERR messaging mechanism. Other types of error conditions can still be signaled via SERR
messaging independent of this bit’s state.
1 = Enable. Address and data parity errors detected on PCI_B are reported via the HI SERR
messaging mechanism, if further enabled by SERRE1.
86
Intel^® 82845GE/82845PE Datasheet