82845PE Datasheet, PDF (112/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Functional Description
5.2.2.1
Configuration Mechanism for DIMMs
Detection of the type of SDRAM installed on the DIMM is supported via Serial Presence Detect
(SPD) mechanism as defined in the JEDEC DIMM specification. This uses the SCL, SDA, and
SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special
programmable modes are provided on the (G)MCH for detecting the size and type of memory
installed. Type and size detection must be done via the serial presence detection pins and is
required to configure the (G)MCH.
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the (G)MCH SDRAM registers must
be initialized. The (G)MCH must be configured for operation with the installed memory types.
Detection of memory type and size is done via the System Management Bus (SMB) interface on
the ICH4. This two-wire bus is used to extract the SDRAM type and size information from the
Serial Presence Detect port on the SDRAM DIMMs. SDRAM DIMMs contain a 5-pin Serial
Presence Detect interface, including SCL (serial clock), SDA (serial data), and SA[2:0]. Devices
on the SMBus bus have a 7-bit address. For the SDRAM DIMMs, the upper four bits are fixed at
1010. The lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected to the
System Management Bus on the ICH4. Thus, data is read from the Serial Presence Detect port on
the DIMMs via a series of I/O cycles to the ICH4. BIOS needs to determine the size and type of
memory used for each of the rows of memory to properly configure the (G)MCH memory
interface.
SMBus Configuration and Access of the Serial Presence Detect Ports
For more details, refer to the Intel^® 82801DB I/O Controller Hub 4 (ICH4) Datasheet.
Memory Register Programming
This section provides an overview of how the required information for programming the SDRAM
registers is obtained from the Serial Presence Detect ports on the DIMMs. The Serial Presence
Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a
row by row basis), SDRAM Timings, Row Sizes, and Row Page Sizes. Table 5-3 lists a subset of
the data available through the on board Serial Presence Detect ROM on each DIMM. Table 5-3 is
only a subset of the defined SPD bytes on the DIMMs. These bytes collectively provide enough
data for programming the (G)MCH SDRAM registers.
Table 5-3. Data Bytes on DIMM Used for Programming DRAM Registers
Byte
2
3
4
5
11
12
17
Function
Memory Type (DDR SDRAM)
Number of Row Addresses, not counting Bank Addresses
Number of Column Addresses
Number of banks of SDRAM (single- or double-sided DIMM)
ECC, non-ECC ((G)MCH does not support ECC)
Refresh rate
Number of Banks on each device
112
Intel^® 82845GE/82845PE Datasheet