82845PE Datasheet, PDF (27/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Signal Description
2.4.2 AGP Flow Control Signals
2.4.3
Signal Name
GRBF#
GWBF#
Type
I
AGP
I
AGP
Description
Read Buffer Full: This signal indicates if the master is ready to accept previously
requested low priority read data. When GRBF# is asserted, the (G)MCH is not
allowed to return low priority read data to the AGP master. GRBF# is only
sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data, it is not required to
implement this signal.
Write Buffer Full: This signal indicates if the master is ready to accept fast write
data from the (G)MCH. When GWBF# is asserted, the (G)MCH is not allowed to
drive fast write data to the AGP master. GWBF# is only sampled at the beginning
of a cycle.
If the AGP master is always ready to accept fast write data, it is not required to
implement this signal.
AGP Status Signals
Signal Name
GST_[2:0]
Type
O
AGP
Description
Status: GST_[2:0] provide information from the arbiter to an AGP Master on
what it may do. GST_[2:0] only have meaning to the master when its GGNT#
is asserted. When GGNT# is deasserted, these signals have no meaning and
must be ignored. GST_[2:0] are always an output from the (G)MCH and an
input to the master.
000 = Previously requested low priority read data is being returned to the
master
001 = Previously requested high priority read data is being returned to the
master.
010 = The master is to provide low priority write data for a previously queued
Write command.
011 = The master is to provide high priority write data for a previously queued
Write command.
100 = Reserved
101 = Reserved
110 = Reserved
111= The master has been given permission to start a bus transaction. The
master may queue AGP requests by asserting PIPE# or start a PCI
transaction by asserting FRAME#.
Intel^® 82845GE/82845PE Datasheet
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