82845PE Datasheet, PDF (121/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Functional Description
Reads
• Read cycle is immediately retried (the (G)MCH retries the read cycle in three PCI clocks from
GFRAME# driven active) due to a pending processor-AGP or hub interface-AGP write
transaction. It is further handled using the Delayed Transaction mechanism described in a later
section. This can occur as a result of the processor posting memory write cycles to the AGP or
the (G)MCH storing a processor to AGP write cycle in the deferred queue. The SDRAM read
cycle is immediately retried and the (G)MCH initiates the Delayed Transaction activity by
issuing a single snoop on the processor bus. The Delayed transaction cannot complete until
after the pending processor-AGP or hub interface-AGP transactions have been completed on
the AGP.
• Processor-to-AGP write or hub interface-to-AGP write is posted after the processing of AGP/
PCI to SDRAM read has started but prior to data being returned. This scenario can occur due
to the level of concurrency supported by (G)MCH. The AGP/PCI cycle will be retried as soon
as condition is recognized and it is further handled as a Delayed Transaction.
• Processor-to-AGP read request is internally pending when an AGP-DRAM read is issued or
processor-to-AGP read request is issued after an AGP-DRAM read request is generated. The
AGP cycle is retried based on 32-clock timeout. The timer is triggered at the point when
internally pending processor-to-AGP read request is observed.
• Processor-to-AGP write occurs after AGP-to-SDRAM memory read line or memory read
multiple data has been returned. The (G)MCH stops snooping ahead when the processor-to-
AGP write occurs and the (G)MCH disconnects when the last DWord of data is read (between
2 and 3 cachelines).
• AGP-DRAM burst is disconnected after crossing the 4-KB address boundary.
• AGP-DRAM burst is disconnected if consecutive data phase can not complete within 8 clocks
and there is an AGP non-snoopable request or host bridge-to-AGP request pending.
• AGP-DRAM burst is disconnected after crossing a 2-KB address. No snoop is generated into
next 2-KB page.
Writes
• If the AGP/PCI Inbound buffer is full, the (G)MCH retries initial write request in the presence
of a pending AGP request issued by the AGP master using enhanced AGP protocol (i.e., non-
snoopable) or in the presence of host bridge request for AGP ownership (when there is a
pending processor-AGP or hub interface-AGP transaction).
• If the AGP Inbound buffer is full and there is no pending AGP non-snoopable request and no
host bridge request, the (G)MCH inserts wait-states. It retries as soon as AGP non-snoopable
request is generated or an internal host bridge to AGP request is generated.
• If AGP Inbound buffers become full during the burst, the (G)MCH disconnects within 8 clocks
if there is an AGP non-snoopable request or host bridge-to-AGP request present.
An AGP-DRAM burst is disconnected after crossing the 2-KB address boundary.
Intel^® 82845GE/82845PE Datasheet
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