82845PE Datasheet, PDF (80/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.2.9
HDR1—Header Type Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Eh
01h
RO
8 bits
This register identifies the header layout of the configuration space. No physical register exists at
this location.
3.5.2.10
Bit
Description
7:0
Header Type Register (HDR). This read only field always returns 01 to indicate that (G)MCH Device
1 is a single function device with bridge header layout.
PBUSN1—Primary Bus Number Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
18h
00h
RO
8 bits
This register identifies that “virtual” PCI-to-PCI bridge is connected to bus #0.
3.5.2.11
Bit
Description
Primary Bus Number (BUSN). Configuration software typically programs this field with the number
7:0 of the bus on the primary side of the bridge. Since Device 1 is an internal device and its primary bus
is always 0, these bits are read only and are hardwired to 0.
SBUSN1—Secondary Bus Number Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
19h
00h
R/W
8 bits
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-to-PCI
bridge (i.e., to PCI_B/AGP). This number is programmed by the PCI configuration software to
allow mapping of configuration cycles to PCI_B/AGP.
Bit
Description
7:0
Secondary Bus Number (BUSN). This field is programmed by configuration software with the bus
number assigned to PCI_B.
80
Intel^® 82845GE/82845PE Datasheet