82845PE Datasheet, PDF (73/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.1.34
ERRCMD—Error Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
CA–CBh
0000h
RO, R/W
16 bits
This register controls the (G)MCH responses to various system errors. Since the (G)MCH does not
have a SERR# signal, SERR messages are passed from the (G)MCH to the ICH4 over the hub
interface. When a bit in this register is set, a SERR message will be generated on the hub interface
when the corresponding flag is set in the ERRSTS register. The actual generation of the SERR
message is globally enabled for Device 0 via the PCI command register.
Bit
Description
15:10
9
8:7
6
5
4
3
2
1:0
Intel Reserved.
SERR on Non-DRAM Lock (LCKERR).
1 = Disable.
1 = Enable. The (G)MCH generates a HI SERR special cycle when a processor lock cycle is
detected that does not hit SDRAM.
Intel Reserved.
SERR on Target Abort on HI Exception (TAHLA).
0 = Disable.
1 = Enable. The (G)MCH generates an SERR special cycle over HI when a (G)MCH originated hub
interface cycle is completed with a Target Abort completion packet or special cycle.
SERR on Detecting HI Unimplemented Special Cycle (HIAUSCERR). SERR messaging for
Device 0 is globally enabled in the PCICMD register.
0 = Disable. The (G)MCH does not generate an SERR message for this event.
1 = Enable. The (G)MCH generates an SERR message over HI when an Unimplemented Special
Cycle is received on the HI.
SERR on AGP Access Outside of Graphics Aperture (OOGF).
0 = Disable. Reporting of this condition is disabled.
1 = Enable. The (G)MCH generates an SERR special cycle over HI when an AGP access occurs to
an address outside of the graphics aperture.
SERR on Invalid AGP Access (IAAF).
0 = Disable. Invalid AGP Access condition is not reported.
1 = Enable. The (G)MCH generates an SERR special cycle over HI when an AGP access occurs to
an address outside of the graphics aperture and either to the 640 KB –1 MB range or above the
top of memory. I
SERR on Invalid Translation Table Entry (ITTEF).
0 = Disable. Reporting of this condition is disabled.
1 = Enable. The (G)MCH generates an SERR special cycle over HI when an invalid translation table
entry was returned in response to an AGP access to the graphics aperture.
Intel Reserved.
Intel^® 82845GE/82845PE Datasheet
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