82845PE Datasheet, PDF (68/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.1.26
AGPCMD—AGP Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
A8–ABh
00000000h
RO, R/W
32 bits
This register provides control of the AGP operational parameters.
3.5.1.27
Bit
31:10
9
8
7:5
4
3
2:0
Description
Intel Reserved.
SideBand Addressing Enable (SBAEN).
0 = Disable.
1 = Enable.
AGP Enable (AGPEN). When this bit is reset to 0, the (G)MCH will ignore all AGP operations,
including the sync cycle. Any AGP operations received while this bit is set to 1 will be serviced even
if this bit is reset to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA
command being delivered in 1X mode the command will be issued. When this bit is set to 1 the
(G)MCH will respond to AGP operations delivered via PIPE#, or to operations delivered via SBA if
the AGP Side Band Enable bit is also set to 1.
Intel Reserved.
Fast Write Enable (FWEN).
0 =Disable. When this bit is 0 or when the data rate bits are set to 1X mode, the Memory Write
transactions from the (G)MCH to the AGP master use standard PCI protocol.
1 =Enable. The (G)MCH uses the Fast Write protocol for Memory Write transactions from the
(G)MCH to the AGP master. Fast Writes will occur at the data transfer rate selected by the data
rate bits (2:0) in this register.
Intel Reserved.
Data Rate Enable (DRATE). The setting of these bits determines the AGP data transfer rate. One
(and only one) bit in this field must be set to indicate the desired data transfer rate. The same bit
must be set on both master and target.
001 = 1X Transfer Mode
010 = 2X Transfer Mode
100 = 4X Transfer Mode
AGPCTRL—AGP Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
B0–B3h
00000000h
RO, R/W
32 bits
This register enables additional control of the AGP interface.
Bit
Description
31:8 Intel Reserved.
GTLB Enable (GTLBEN).
7 0 =Disable (default). The GTLB is flushed by clearing the valid bits associated with each entry.
1 =Enable. Normal operations of the Graphics Translation Lookaside Buffer.
6:0 Intel Reserved.
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Intel^® 82845GE/82845PE Datasheet