82845PE Datasheet, PDF (44/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
Figure 3-3. Configuration Mechanism Type 1 Configuration Address to PCI Address Mapping
31 30
24 23
16 15
11 10
87
21 0
CONFIG_ADDRESS 1 Reserved Bus Number Device Number Function Number Reg. Index X X
PCI Address
AD[31:0]
0
31
Bus Number Device Number Function Number Reg. Index 0 1
24 23
16 15
11 10
87
21 0
To prepare for mapping of the configuration cycles on AGP/PCI_B, the initialization software will
go through the following sequence:
1. Scan all devices residing on the PCI Bus #0 using Type 0 configuration accesses.
2. For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it will
configure the secondary bus of the bridge with the appropriate number and scan further down
the hierarchy. This process includes the configuration of the “virtual” PCI-to-PCI bridges
within the (G)MCH used to map the AGP device’s address spaces in a software specific
manner.
Note:
Although initial AGP platform implementations will not support hierarchical buses residing below
AGP, this specification still must define this capability to support PCI-66 compatibility. Note also
that future implementations of the AGP devices may support hierarchical PCI or AGP-like buses
coming out of the root AGP device.
3.4
3.4.1
I/O Mapped Registers
The (G)MCH contains two registers that reside in the processor I/O address space − the
Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible through the
Configuration Data window.
CONFIG_ADDRESS—Configuration Address Register
I/O Address:
Default Value:
Access:
Size:
0CF8h Accessed as a DWord
00000000h
R/W
32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DWord. A Byte or Word
reference will “pass through” the Configuration Address Register and hub interface onto the
PCI_A bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device
Number, Function Number, and Register Number for which a subsequent configuration access is
intended.
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Intel^® 82845GE/82845PE Datasheet