82845PE Datasheet, PDF (58/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.1.16
DRB[0:3]—DRAM Row Boundary Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
60–63h (64h–6Fh Reserved)
01h
Read/Write
8 bits
The DRAM Row Boundary Register defines the upper boundary address of each DRAM row with
a granularity of 32 MB. Each row has its own single-byte DRB register. For example, a value of 1
in DRB0 indicates that 32 MB of DRAM has been populated in the first row. Since the (G)MCH
supports a total of four rows of memory, only DRB[0:3] are used.
Row0:
Row1:
Row2:
Row3:
64h–6Fh:
60h
61h
62h
63h
Reserved
DRB0 = Total memory in row0 (in 32-MB increments)
DRB1 = Total memory in row0 + row1 (in 32-MB increments)
DRB2 = Total memory in row0 + row1 + row2 (in 32-MB increments)
DRB3 = Total memory in row0 + row1 + row2 + row3 (in 32-MB increments)
Each Row is represented by a byte. Each byte has the following format.
Bit
Description
DRAM Row Boundary Address. This 8-bit value defines the upper and lower addresses for each
7:0 SDRAM row. This 8-bit value is compared against a set of address lines to determine the upper
address limit of a particular row.
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Intel^® 82845GE/82845PE Datasheet