82845PE Datasheet, PDF (36/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Signal Description
2.10 Functional Straps
Signal Name
PSB_SEL
Type
I
Description
PSB Frequency Select: The PSB_SEL is tied to the external BSEL resistor-
divider circuitry. The value of the PSB_SEL pin reflects the PSB frequency. The
PSB runs at 400 MHz when PSB_SEL is a 0 and runs at 533 MHz when PSB_SEL
is a 1.
2.11 Intel^® (G)MCH Sequencing Requirements
Power Plane and Sequencing Requirements:
• Clock Valid Timing:
• GCLKIN must be valid at least 10 µs prior to the rising edge of PWROK.
• HCLKN/HCLKP must be valid at least 10 µs prior to the rising edge of RSTIN#.
• There is no DREFCLK timing requirements relative to reset.
Figure 2-2. Intel^® (G)MCH System Clock and Reset Requirements
POWER
PWROK
RSTIN#
GCLKIN
HCLKN/HCLKP
~100 ms
10 µs
min
~1 ms
valid
10 µs
min
valid
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Intel^® 82845GE/82845PE Datasheet