82845PE Datasheet, PDF (87/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
The bit field definitions for VGAEN and MDAP are detailed in Table 3-4.
Table 3-4. VGAEN and MDAP Bit Definitions
VGAEN
0
0
1
1
MDAP
0
1
0
1
Description
All References to MDA and VGA space are routed to hub interface.
Illegal combination
All VGA references are routed to this bus. MDA references are routed to the hub
interface.
All VGA references are routed to this bus. MDA references are routed to hub interface.
3.5.2.22
ERRCMD1—Error Command Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
40h
00h
R/W
8 bits
Bit
Description
7:1 Reserved.
SERR on Receiving Target Abort (SERTA). SERR messaging for Device 1 is globally enabled in
the PCICMD1 register.
0
0 = Disable. The (G)MCH does not assert an SERR message upon receipt of a target abort on
PCI_B.
1 = Enable. The (G)MCH generates an SERR message over the hub interface upon receiving a
target abort on PCI_B.
Intel^® 82845GE/82845PE Datasheet
87