82845PE Datasheet, PDF (92/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.3.6
3.5.3.7
3.5.3.8
CC—Class Code Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
09h−0Bh
030000h
RO
24 bits
This register contains the device programming interface information related to the Sub-Class Code
and Base Class Code definition for the IGD. This register also contains the Base Class Code and
the function sub-class in relation to the Base Class Code.
Bit
23:16
15:8
7:0
Description
Base Class Code (BASEC). 03=Display controller
Sub-Class Code (SCC).
Function 0: 00h=VGA compatible or 80h=Non VGA; based on Device 0 GC bit 1.
Function 1: 80h=Non VGA;
Programming Interface (PI). 00h=Hardwired as a Display controller.
CLS—Cache Line Size Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
0Ch
00h
RO
8 bits
The IGD does not support this register as a PCI slave.
Bit
Description
Cache Line Size (CLS). This field is hardwired to zeros. The IGD, as a PCI compliant master, does
7:0 not use the Memory Write and Invalidate command and, in general, does not perform operations
based on cache line size.
MLT2—Master Latency Timer Register (Device 2)
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
RO
8 bits
The IGD does not support the programmability of the master latency timer because it does not
perform bursts.
Bit
Description
7:0 Master Latency Timer Count Value. Hardwired to zeros.
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Intel^® 82845GE/82845PE Datasheet