82845PE Datasheet, PDF (41/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
Logically, the ICH4 appears as multiple PCI devices within a single physical component also
residing on PCI bus #0. One of the ICH4 devices is a PCI-to-PCI bridge. Logically, the primary
side of the bridge resides on PCI #0 while the secondary side is the standard PCI expansion bus.
Note: A physical PCI bus #0 does not exist and that the hub interface and the internal devices in the
(G)MCH and ICH4 logically constitute PCI Bus #0 to configuration software.
Figure 3-1. Conceptual Intel^® 845GE/845PE Chipset Platform PCI Configuration Diagram
Processor
PCI Configuration Window
in I/O Space
Host-to-AGP
Bridge; Bus #0,
Device 1
GMCH/MCH
Integrated
Graphics Device;
Bus #0,
Device 2
(82845GE only)
Hub
Interface
DRAM Control/Hub
Interface Device;
Bus #0,
Device 0
Intel^® ICH4
3.3
Routing Configuration Accesses
The (G)MCH supports two bus interfaces: Hub interface and AGP/PCI. PCI configuration cycles
are selectively routed to one of these interfaces. The (G)MCH is responsible for routing PCI
configuration cycles to the proper interface. PCI configuration cycles to ICH4 internal devices and
Primary PCI (including downstream devices) are routed to the ICH4 via the hub interface. AGP/
PCI_B configuration cycles are routed to AGP. The AGP/PCI_B interface is treated as a separate
PCI bus from the configuration point of view. Routing of configuration accesses to AGP/PCI_B is
controlled via the standard PCI-to-PCI bridge mechanism using information contained within the
Primary Bus Number, the Secondary Bus Number, and the Subordinate Bus Number registers of
the corresponding PCI-to-PCI bridge device.
A detailed description of the mechanism for translating processor I/O bus cycles to configuration
cycles on one of the two buses is described in the following sections.
Intel^® 82845GE/82845PE Datasheet
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