82845PE Datasheet, PDF (3/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Contents
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Introduction ........................................................................................................... 13
1.1 Terminology ...................................................................................................13
1.2 Related Documents .......................................................................................14
1.3 Intel^® 845GE / 845PE Chipset System Overview ..........................................15
1.4 Intel^® 82845GE GMCH / 82845PE MCH Overview .......................................17
1.4.1 Host Interface....................................................................................17
1.4.2 System Memory Interface .................................................................17
1.4.3 Hub Interface ....................................................................................17
1.4.4 Multiplexed AGP and Intel^® DVO Port Interface ...............................18
1.4.5 Graphics Overview (Intel^® 82845GE only)........................................18
1.4.6 Display Interfaces (Intel^® 82845GE only) .........................................19
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Signal Description ..............................................................................................21
2.1 Host Interface Signals....................................................................................23
2.2 DDR SDRAM Interface ..................................................................................25
2.3 Hub Interface .................................................................................................26
2.4 AGP Interface Signals....................................................................................26
2.4.1 AGP Addressing Signals...................................................................26
2.4.2 AGP Flow Control Signals ................................................................27
2.4.3 AGP Status Signals ..........................................................................27
2.4.4 AGP Strobes .....................................................................................28
2.4.5 PCI Signals–AGP Semantics............................................................29
2.4.6 PCI Pins during PCI Transactions on AGP Interface ........................30
2.5 Multiplexed DVO Device Signal Interfaces (Intel^® 82845GE only) ................30
2.5.1 Intel^® DVO Signal Name to AGP Signal Name Pin
Mapping (Intel^® 82845GE only) ........................................................32
2.6 Analog Display (Intel^® 82845GE only) ...........................................................33
2.7 Clocks, Reset, and Miscellaneous Signals ....................................................34
2.8 RCOMP, VREF, VSWING Signals.................................................................34
2.9 Power and Ground Signals ............................................................................35
2.10 Functional Straps ...........................................................................................36
2.11 Intel^® (G)MCH Sequencing Requirements ....................................................36
2.12 Reset States ..................................................................................................37
2.12.1 Full and Warm Reset States .............................................................37
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Register Description..........................................................................................39
3.1 Register Terminology.....................................................................................39
3.2 Platform Configuration ...................................................................................40
3.3 Routing Configuration Accesses....................................................................41
3.3.1 Standard PCI Bus Configuration Mechanism ...................................42
3.3.2 PCI Bus #0 Configuration Mechanism ..............................................42
3.3.3 Primary PCI and Downstream Configuration Mechanism.................42
3.3.4 AGP/PCI_B Bus Configuration Mechanism ......................................42
3.4 I/O Mapped Registers ....................................................................................44
3.4.1 CONFIG_ADDRESS—Configuration Address Register ...................44
3.4.2 CONFIG_DATA—Configuration Data Register ................................45
3.5 Intel^® (G)MCH Internal Device Registers ......................................................46
3.5.1 DRAM Controller/Host-Hub Interface Device Registers (Device 0) ..46
Intel^® 82845GE/82845PE Datasheet
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