82845PE Datasheet, PDF (72/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.1.33 ERRSTS—Error Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
C8–C9h
0000h
R/WC
16 bits
This register is used to report various error conditions via the SERR HI messaging mechanism. An
SERR HI message is generated on a zero to one transition of any of these flags (if enabled by the
ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR is
enabled and generated.
Note: Software clears bits in this register by writing a 1 to the bit position.
Bit
15:10
9
8
7
6
5
4
3
2
1:0
Description
Intel Reserved.
Non-DRAM Lock Error (NDLOCK).
1 = The (G)MCH has detected a lock operation to memory space that did not map into SDRAM.
Software Generated SMI Flag.
1 = This indicates the source of an SMI was a Software SMI Trigger.
Intel Reserved.
SERR on HI Target Abort (TAHLA).
1 = The (G)MCH has detected that a (G)MCH originated hub interface cycle was terminated with a
Target Abort completion packet or special cycle.
(G)MCH Detects Unimplemented HI Special Cycle (HIAUSC).
1 = The (G)MCH detected an Unimplemented Special Cycle on the hub interface.
AGP Access Outside of Graphics Aperture Flag (OOGF).
1 = AGP access occurred to an address that is outside of the graphics aperture range.
Invalid AGP Access Flag (IAAF).
1 = AGP access was attempted outside of the graphics aperture and either to the 640 KB –1 MB
range or above the top of memory.
Invalid Graphics Aperture Translation Table Entry (ITTEF).
1 = An invalid translation table entry was returned in response to an AGP access to the graphics
aperture.
Intel Reserved.
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Intel^® 82845GE/82845PE Datasheet