82845PE Datasheet, PDF (110/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Functional Description
5.1.2
5.1.3
When the processor or the (G)MCH drives data, each 16-bit segment is analyzed. If more than 8 of
the 16 signals would normally be driven low on the bus, the corresponding DINV# signal is
asserted and the data is inverted prior to being driven on the bus. When the processor or the
(G)MCH receives data, it monitors DINV[3:0]# to determine if the corresponding data segment
should be inverted.
System Bus Interrupt Delivery
Pentium 4 processors support system bus interrupt delivery. They do not support the APIC serial
bus interrupt delivery mechanism. Interrupt-related messages are encoded on the system bus as
“Interrupt Message Transactions.” In an 845GE/845PE chipset platform, system bus interrupts can
originate from the processor on the system bus, or from a downstream device on hub interface, or
AGP. In the later case the (G)MCH drives the “Interrupt Message Transaction” on the system bus.
In an 845GE/845PE chipset platform, the ICH4 contains IOxAPICs, and its interrupts are
generated as upstream hub interface memory writes. Furthermore, PCI Local Bus Specification,
Revision 2.2 defines MSIs (Message Signaled Interrupts) that are also in the form of memory
writes. A PCI Local Bus Specification, Revision 2.2 device can generate an interrupt as an MSI
cycle on it’s PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI can be
directed to the IOxAPIC, which in turn generates an interrupt as an upstream hub interface memory
write. Alternatively, the MSI can be directed directly to the system bus. The target of an MSI is
dependent on the address of the interrupt memory write. The (G)MCH forwards inbound hub
interface and AGP (PCI semantic only) memory writes to address 0FEEx_xxxxh, to the system bus
as “Interrupt Message Transactions.”
Upstream Interrupt Messages
The (G)MCH accepts message based interrupts from AGP (PCI semantics only) or its hub
interface, and forwards them to the system bus as Interrupt Message Transactions. The interrupt
messages presented to the (G)MCH are in the form of memory writes to address 0FEEx_xxxxh. At
the hub interface or AGP interface, the memory write interrupt message is treated like any other
memory write; it is either posted into the inbound data buffer (if space is available) or retried (if
data buffer space is not immediately available). Once posted, the memory write from AGP or the
hub interface, to address 0FEEx_xxxxh, is decoded as a cycle that needs to be propagated by the
(G)MCH to the system bus as an Interrupt Message Transaction.
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Intel^® 82845GE/82845PE Datasheet