82845PE Datasheet, PDF (83/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.2.16
SSTS1—Secondary Status Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1Eh
02A0h
RO, R/WC
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with
secondary side (i.e., PCI_B/AGP side) of the “virtual” PCI-to-PCI bridge embedded within the
(G)MCH.
Bit
Description
Detected Parity Error (DPE)—R/WC.
15 ^{0 = Software sets DPE1 to 0 by writing a 1 to this bit.}
1 = Indicates (G)MCH’s detection of a parity error in the address or data phase of PCI_B/AGP bus
transactions.
14
Received System Error (RSE)—RO. Hardwired to 0. (G)MCH does not have an SERR# signal pin
on the AGP interface.
Received Master Abort Status (RMAS)—R/WC.
13 0 = Software resets this bit to 0 by writing a 1 to it.
1 = The (G)MCH terminated a Host-to-PCI_B/AGP with an unexpected master abort.
Received Target Abort Status (RTAS)—R/WC.
12 0 = Software resets RTAS1 to 0 by writing a 1 to it.
1 = The (G)MCH-initiated transaction on PCI_B/AGP is terminated with a target abort.
11
Signaled Target Abort Status (STAS)—RO. Hardwired to a 0. The (G)MCH does not generate
target abort on PCI_B/AGP.
DEVSEL# Timing (DEVT)—RO. Hardwired to a 00. This field indicates the timing of the DEVSEL#
10:9 signal when the (G)MCH responds as a target on PCI_B/AGP. It is hardwired to 01b (medium) to
indicate the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.
8
Master Data Parity Error Detected (DPD)—RO. Hardwired to 0. The (G)MCH does not implement
G_PERR# signal on PCI_B.
7
Fast Back-to-Back (FB2B)—RO. Hardwired to 1. The (G)MCH, as a target, supports fast back-to-
back transactions on PCI_B/AGP.
6 Reserved.
5
66/60 MHz Capability (CAP66)—RO. Hardwired to 1. Indicates that the AGP/PCI_B bus is capable
of 66 MHz operation.
4:0 Reserved.
Intel^® 82845GE/82845PE Datasheet
83