82845PE Datasheet, PDF (52/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.1.8
3.5.1.9
MLT—Master Latency Timer Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
RO
8 bits
Device 0 in the (G)MCH is not a PCI master. Therefore this register is not implemented.
Bit
7:0 Reserved.
Description
HDR—Header Type Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
0Eh
00h
RO
8 bits
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit
Description
7:0
PCI Header (HDR). This field always returns 0 to indicate that the (G)MCH is a single function device
with standard header layout.
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Intel^® 82845GE/82845PE Datasheet