82845PE Datasheet, PDF (114/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Functional Description
5.3
5.3.1
5.3.1.1
AGP Interface
See the Accelerated Graphics Port Interface Specification, Revision 2.0 for additional details about
the AGP interface.
Overview
For the 82845PE MCH, the AGP signals are non-multiplexed. For the 82845GE GMCH, the AGP
signals are multiplexed with two DVO ports. The GMCH’s DVO ports can support single-channel
DVO devices or can combine to support dual-channel devices, supporting higher resolutions and
refresh rates. When an external AGP device is used, the multiplexed DVO ports are not available,
as the GMCH’s IGD will be disabled. For more information on the multiplexed DVO interface,
refer to Section 5.5.
The (G)MCH supports 1.5 V AGP 1X/2X/4X devices. The AGP signal buffers have one mode of
operation; 1.5 V drive/receive (not 3.3 V tolerant). The (G)MCH supports 4X (266 MT/s) clocking
transfers for read and write data, and sideband addressing. The (G)MCH has a 32-deep AGP
request queue.
AGP semantic transactions to system SDRAM do not get snooped and are, therefore, not coherent
with the processor caches. PCI semantic transactions on AGP to system SDRAM are snooped.
AGP semantic accesses to the hub interface/PCI are not supported. PCI semantic accesses from an
AGP master to hub interface are also not supported.
Lock Behavior
If the processor has established a LOCK to AGP, the (G)MCH immediately retries incoming
FRAME# cycles. The reads will not be processed internally as a delayed transaction.
If the processor has established a LOCK to another resource other than AGP, the (G)MCH will
accept incoming FRAME# cycles based on the other retry/disconnect rules. Since snoops cannot be
generated to the processor while a LOCK is outstanding, eventually the (G)MCH’s PCI interface
backs up.
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Intel^® 82845GE/82845PE Datasheet