82845PE Datasheet, PDF (74/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.1.35
3.5.1.36
3.5.1.37
3.5.1.38
SMICMD—SMI Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
CC–CDh
0000h
RO, R/W
16 bits
This register enables various errors to generate a SMI message via the hub interface.
Bit
15:0 Intel Reserved.
Description
SCICMD—SCI Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
CE–CDh
0000h
RO, R/W
16 bits
This register enables various errors to generate a SMI message via the hub interface.
Bit
15:0 Intel Reserved.
Description
SKPD—Scratchpad Data Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
DEh
0000h
R/W
16 bits
Bit
15:0
Description
Scratchpad (SCRTCH). These bits are simply R/W storage bits that have no effect on the (G)MCH
functionality.
CAPREG—Capability Identification Register (Device 0)
Address Offset:
Default:
Access:
Size
E4h–E8h
0x_x105_A009h
RO
40 bits
Bit
39:28
27:24
23:16
15:8
7:0
Description
Part Identifier.
214h = 82845GE
216h = 82845PE
CAPREG Version. This field has the value 0001b to identify the first revision of the CAPREG
definition.
Cap_length. This field has the value 05h indicating the structure length.
Next_Pointer. This field has the value A0h pointing to the next capabilities register, AGP Capability
Identifier Register (ACAPID). If AGP is disabled (IGDIS = 0), since this is the last pointer in the
device, it is set to 00h signifying the end of the capabilities linked list.
CAP_ID. This field has the value 09h to identify the CAP_ID assigned by the PCI SIG for Vendor
Dependent CAP_PTR.
74
Intel^® 82845GE/82845PE Datasheet