82845PE Datasheet, PDF (29/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Signal Description
2.4.5
PCI Signals–AGP Semantics
PCI signals are redefined when used in AGP transactions carried using AGP protocol extension.
For transactions on the AGP interface carried using PCI protocol, these signals completely
preserve PCI Local Bus Specification, Revision 2.1 semantics. The exact roles of all PCI signals
during AGP transactions are defined below.
Signal Name
Type
Description
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GDEVSEL#
GREQ#
GGNT#
GAD_[31:0]
GC/BE_[3:0]#
GPAR /
ADD_DETECT
(82845GE only)
I/O s/t/s
AGP
I/O s/t/s
AGP
I/O s/t/s
AGP
I/O s/t/s
AGP
I/O s/t/s
AGP
I
AGP
O
AGP
I/O AGP
I/O AGP
I/O AGP
Frame: GFRAME# is an output from the (G)MCH during Fast Writes.
Initiator Ready: GIRDY# indicates the AGP compliant master is ready to
provide all write data for the current transaction. Once GIRDY# is asserted for a
write operation, the master is not allowed to insert wait-states. The assertion of
GIRDY# for reads indicates that the master is ready to transfer to a subsequent
block (4 clocks) of read data. The master is never allowed to insert a wait-state
during the initial data transfer (first 4 clocks) of a read transaction. However, it
may insert wait-states after each 4 clock block is transferred.
NOTE: There is no GFRAME# – GIRDY# relationship for AGP transactions.
Target Ready: GTRDY# indicates the AGP compliant target is ready to provide
read data for the entire transaction (when the transfer size is less than or equal
to 4 clocks) or is ready to transfer the initial or subsequent block (4 clocks) of
data when the transfer size is greater than 4 clocks. The target is allowed to
insert wait-states after each block (4 clocks) is transferred on both read and
write transactions.
Stop: Same as PCI. Not used by AGP.
Device Select: Same as PCI. Not used by AGP.
Request: Same as PCI. This signal is used to request access to the bus to
initiate a PCI or AGP request.
Grant: Same meaning as PCI but additional information is provided on
GST[2:0]. The additional information indicates that the selected master is the
recipient of previously requested read data (high or normal priority); it is to
provide write data (high or normal priority), for a previously queued write
command or has been given permission to start a bus transaction (AGP or PCI).
Address: Same as PCI.
Command/Byte Enable: These signals have a slightly different meaning for
AGP. Provides command information (different commands than PCI) when
requests are being queued when using GPIPE#. Provide valid byte information
during AGP write transactions and are not used during the return of read data.
PAR: Same as PCI. Not used on AGP transactions but used during PCI
transactions as defined by the PCI Local Bus Specification, Revision 2.1.
ADD_DETECT (82845GE only): The 82845GE GMCH multiplexes an
ADD_DETECT signal with the GPAR signal on the AGP bus. This signal acts as
a strap and indicates whether the interface is in AGP or DVO mode. The
82845GE GMCH has an internal pull-up on this signal that will naturally pull it
high. If an ADD card is present, the signal will be pulled low on the ADD card
and the AGP/DVO multiplex select bit in the GMCHCFG register will be set to
DVO mode. Motherboards that use this interface in a DVO down scenario (no
AGP connector) should have a pull-down resistor on ADD_DETECT.
NOTES:
1. PCIRST# from the ICH4 is connected to RSTIN# and is used to reset AGP interface logic within the (G)MCH.
The AGP agent will also typically use PCIRST# provided by the ICH4 as an input to reset its internal logic.
2. The LOCK# signal is not supported on the AGP Interface (even for PCI operations).
3. The PERR# and SERR# signals are not supported on the AGP interface.
Intel^® 82845GE/82845PE Datasheet
29