82845PE Datasheet, PDF (51/176 Pages) Intel Corporation – 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)

Register Description
3.5.1.5
3.5.1.6
3.5.1.7
RID—Revision Identification Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
08h
See table below
RO
8 bits
This register contains the revision number of the (G)MCH Device 0.
Bit
Description
Revision Identification Number (RID). This is an 8-bit value that indicates the revision identification
number for the (G)MCH Device 0.
82845GE GMCH
7:0
03h = B1 Stepping
82845PE GMCH
02h = B0 Stepping
SUBC—Sub-Class Code Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
0Ah
00h
RO
8 bits
This register contains the Sub-Class Code for the (G)MCH Device 0.
Bit
Description
Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of Bridge into which the
7:0 ^{(G)MCH falls.}
00h = Host Bridge.
BCC—Base Class Code Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
0Bh
06h
RO
8 bits
This register contains the Base Class Code of the (G)MCH Device 0.
Bit
Description
Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the
7:0 ^(G)MCH.
06h = Bridge device.
Intel^® 82845GE/82845PE Datasheet
51