PXF4333 Datasheet, PDF (77/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

ABM-3G
PXF 4333 V1.1
Functional Description
3.4.2.2 Scheduler Block
Each Scheduler Block (SB) is a cascade of two scheduling levels, a combination of
Weighted Fair Queueing (WFQ) and Round Robin (RR) schedulers in the first stage,
followed by a priority scheduler in the second stage as shown in Figure 3-22. An
arbitrary number of queues from a maximum of 8191 can be assigned to each scheduler
input at stage 1. (Queue 0 is reserved for the common real-time bypass).
Real-Time Traffic
(e.g. CBR, rt-VBR)
Scheduler #j
optional PCR or VBR Shaper
R
(1)
R
highest
priority
Non Real-Time,
Guaranteed Rate
Traffic
(e.g. nrt-VBR, ABR,
GFR, UBR+)
Non Real-Time,
Best Effort
Traffic
(e.g. UBR)
W0
W1
W
F
Q
Wn
configured output rate
(2)
R
(3)
R
lowest
priority
Logical
Queues
Multiplexers Wi: WFQ Weight Factor
Figure 3-22 Scheduler Block Structure
Scheduler Blocks are the principal queue scheduler concept for QoS differentiation.
Together with the buffer manager concept of traffic classes, various QoS objectives can
be met.
3.4.2.2.1 Priority Scheduler
The priority scheduler implemented in the scheduler block of the ABM-3G has three
priority levels. As long as there are buffered cells destined to pass at priority 1, only these
cells are served. Otherwise, buffered cells destined to pass at priority 2 are served. Only
when there are neither priority 1 nor priority 2 cells buffered, then cells from priority 3 are
allowed to pass. As a result the available bandwidth for priority 1 traffic is the total output
bandwidth. The available bandwidth for priority 2 and priority 3 traffic is the leftover
bandwidth from the next higher priority level respectively.
Chapter 4.2.2.7 provides the details on the mapping of queues to the 3 priority levels.
Data Sheet
77
2001-12-17