PXF4333 Datasheet, PDF (275/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

ABM-3G
PXF 4333 V1.1
Register Description
Register 82 USCEN5/DSCEN5
Upstream/Downstream Scheduler Block Enable 5 Registers
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
USCEN5
AD_H
DSCEN5 C5_H
Written by CPU for global Scheduler configuration
Bit
15
14
13
12
11
10
9
8
SchedEn(95:88)
Bit
7
6
5
4
3
2
1
0
SchedEn(87:80)
SchedEn(95:80)
Scheduler Block Enable
Each bit position enables/disables the respective Scheduler Block
(95..80):
1
Scheduler Block enabled
0
Scheduler Block disabled
Data Sheet
275
2001-12-17