PXF4333 Datasheet, PDF (312/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

Register 110 MODE1
ABM-3G Mode 1 Register
ABM-3G
PXF 4333 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
MODE1
EE_H
Written and Read by CPU
Bit
15
14
SWRES
0
13
12
CPR(1:0)
11
VC
MERGE
10
INIT
RAM
9
INIT
SDRAM
8
CORE
Bit
7
6
WGS
0
5
4
3
2
1
0
0
BIP8 CRC10 LCItog LCIMOD(1:0)
SWRES
Software Reset (clears automatically after four cycles).
This bit is automatically cleared after execution.
’SWRES’ controls reset of all ABM-3G units.
1
Starts internal reset procedure
(0)
self-clearing
CPR(1:0)
Cell Pointer Ram Size configuration
(see also Table 7-3 "External RAM Sizes" on Page 177)
00
256k pointer entries per direction
(corresponds to 256k cells in each cell storage RAM)
01
128k pointer entries per direction
(corresponds to 128k cells in each cell storage RAM)
10
64k pointer entries per direction
(corresponds to 64k cells in each cell storage RAM)
11
reserved
Note: The Cell Pointer RAM Size should be programmed during
initialization and should not be changed during operation.
Data Sheet
312
2001-12-17