PXF4333 Datasheet, PDF (46/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

3.2
Functional Block Description
ABM-3G
PXF 4333 V1.1
Functional Description
3.2.1 Cell Handler (Upstream/Downstream)
The Cell Handler (CH) units are responsible for the physical data flow of storing and
retrieving cells to/from the respective Cell Storage RAM or insertion and extraction of
Resource Management (RM) cells. Updates to the cell header section or to the cell
contents in case of OAM-RM cells are also performed by the Cell Handler units.
3.2.2 Buffer Manager and Queue Scheduler (Overview)
The Buffer Manager (BM) unit is the central function of the ABM-3G device and handles
the logical data flows for upstream and downstream direction. It utilizes the Queue
Scheduler to coordinate cell emission and a common Cell Pointer RAM (SSRAM) to
administrate cell storage.
Any cell entering the CH unit is reported to the BM unit running the cell acceptance
algorithm. In a first step a cell is classified and associated to the logical resource entities
connection, queue, traffic class and scheduler. Once all associated resources are
determined, the BM runs the cell acceptance algorithm based on the current parameter
sets. As a result of all threshold evaluations the cell is either discarded or accepted and
related counters are updated accordingly. Non-empty queues are reported to the Queue
Scheduler (QS) unit to be scheduled by the associated calendar. In return the QS unit
reports queues to the Buffer Manager that are due for cell transmission in the current cell
slot. Upon a cell emit request for a specific queue the BM requests the Cell Handler to
retrieve and transmit the next cell.
Since the BM and QS units are the central functions of the ABM-3G device they are
described in more detail in chapter “Buffer Manager and Queue Scheduler Details”
on Page 60.
3.2.3 AAL5 Assistant
The AAL5 Assistant unit allows insertion and extraction of AAL5 segmented packets
from and towards the Microprocessor Interface. Supported by the corresponding
software driver, the unit implements an “in-line” SAR function, i.e. one packet is
processed at any time by an SAR function. However, upstream and downstream flow as
well as extraction and insertion are independent functions that may be operationally
interleaved.
For extraction, a Scheduler Block must be associated to the AAL5 Assistant unit and
each queue assigned to this scheduler block must be assigned to a VC-merge group to
guarantee that complete packets are forwarded to the AAL5 Assistant unit. The
scheduler block rates can be adjusted according to the microprocessor interface
bandwidth or the intended CPU load. However, the CPU may extract the payload chunks
at a lower rate which will result in internal scheduler block backpressure. No data loss
Data Sheet
46
2001-12-17