PXF4333 Datasheet, PDF (180/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

Register 19 CLP1DIS
CLP1 Discard Global Threshold Registers
ABM-3G
PXF 4333 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
CLP1DIS 2A_H
Written by CPU
Bit
15
14
13
12
11
10
9
8
DCLP1DIS(13:6)
Bit
7
6
5
4
3
2
1
0
UCLP1DIS(13:6)
UCLP1DIS(13:6)
DCLP1DIS(13:6)
Upstream CLP1 Discard Threshold value
Downstream CLP1 Discard Threshold value
These 8-bit values determine a global 14-bit threshold value
(granularity of 64 cells) that enables discard of low-priority (CLP=’1’)
cells.
The threshold values are compared with the per scheduler low
priority cell counter SBOccLP (Scheduler Block Low Priority
Occupancy) (see Internal Table 4: Scheduler Block Occupancy
Table Transfer Registers SBOC0..SBOC4) and enables all CLP1
related discard thresholds, i.e.:
TCT1.BufCiCLP1(7:0) (Register 34: TCT1)
TCT2.SBCiCLP1(7:0) (Register 35: TCT2)
TCT0.QueueCiCLP1(11:0) (Register 33: TCT0)
As a second condition, CLP1 related discard thresholds are only
effective, if the specific queue that is asked to accept the cell is
associated to a traffic class that has EPD function disabled
(EPDen=’0’, see “Traffic Class Table Transfer Registers TCT0,
TCT1, TCT2, TCT3” on Page 195).
The CPU programs the threshold with a granularity of 64 cells by
right shifting the value by 6:
xCLP1DIS(13:6):= (threshold_value(13:0) >> 6)
Data Sheet
180
2001-12-17