PXF4333 Datasheet, PDF (285/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

Register 90 ERCM1
AVT Table Access Mask Register 1
ABM-3G
PXF 4333 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
ERCM0
CD_H
Written by CPU to control internal table Read/Write
access
Bit
15
14
13
12
11
10
9
8
ERCM1(31:24)
Bit
7
6
5
4
3
2
1
0
ERCM1(23:16)
ERCM1(31:16)
ERC Mask Register 1
ERC Mask Registers 0..1 control the Write access from transfer
registers ERCT0 and ERCT1 to the internal AVT table on a per-bit
selection basis. The mask register bit positions correspond to the
respective transfer registers ERCT0 and ERCT1:
0
The dedicated bit of the transfer register overwrites the
table entry during Write.
Does not affect Read access.
1
The dedicated bit of the transfer register does not
overwrite the table entry during Write.
Does not affect Read access.
Data Sheet
285
2001-12-17