PXF4333 Datasheet, PDF (157/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

ABM-3G
PXF 4333 V1.1
Register Description
1
Test Mode:
The LSB of the QID is inverted to test the QID checking
function. A ’BUFER4’ (Register 101: ISRU, Register 102:
ISRD) interrupt is generated whenever a cell is Read out
from the Cell Buffer RAM.
Note: The respective QID value is stored with each cell when written to the appropriate
queue in the cell storage RAM. The ABM-3G checks the stored QID value
against the supposed QID when a cell is read back from the cell storage RAM.
7.2.2 SDRAM Configuration Registers
Register 2 URCFG/DRCFG
Upstream/Downstream SDRAM Configuration Registers
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0033_H
URCFG
02_H
(Reserved)
DRCFG
12_H
Bit
15
14
13
12
11
10
9
8
Reserved(15:8)
Bit
7
6
5
4
3
2
1
0
Reserved(7:0)
•
Note: These registers are for internal use only. Do not to Write a value different from
the Reset Value 0033_H to Registers URCFG/DRCFG.
Data Sheet
157
2001-12-17