PXF4333 Datasheet, PDF (192/361 Pages) Infineon Technologies AG – ABM 3G ATM Buf fer Manager

Register 30 LCI0
LCI Transfer Register 0
ABM-3G
PXF 4333 V1.1
Register Description
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
LCI0
3B_H
Written and Read by CPU to maintain the LCI table
Bit
15
14
13
12
11
10
9
8
Unused(13:6)
Bit
7
6
5
4
3
2
1
0
Unused(5:0)
CLPT
ABM
core
CLPT
CLP Transparent:
Specifies whether the CLP bit of cells belonging to this connection
is evaluated or not in threshold checks. Valid for both upstream and
downstream cores. Does not affect SBOC counters.
0
CLP bit is evaluated.
1
CLP bit is not evaluated; all cells are treated as high
priority cells assuming CLP=0.
ABMcore
ABM-3G Core Selection:
This bit is valid in Uni-directional Mode only and specifies the core
responsible for cells of this LCI.
0
Scheduler Blocks 0..127 are selected (core 0).
1
Scheduler Blocks 128..255 are selected (core 1).
Data Sheet
192
2001-12-17